In the manufacture of semiconductor devices, photoresist masks are typically employed to protect areas which are not to be treated in a particular processing step, such as etching or implantation. After the processing step is completed, the photoresist is removed, and the next step in the manufacturing process is performed. This is particularly the case for the formation of lightly doped drain (LDD) regions and source/drain regions adjacent a transistor gate. For a given device, it may be necessary to apply and remove photoresist many times during various implant steps, and it is important that after each implant all of the photoresist is completely removed and the wafer surface is cleaned to avoid contamination and defects.
Currently, photoresist is most commonly stripped or “ashed” in plasma reactors which employ an RF discharge to produce oxygen radicals which combine with the hydrocarbons of the photoresist to produce water and carbon dioxide in gaseous form, which makes for easy disposal. Because of the presence of oxygen in a highly charged environment, these plasma processes are highly oxidizing with respect to the silicon surface. After the ash step is complete, the silicon substrate is cleaned with a wet clean step to remove any remaining particle residues.
The area on the semiconductor surface that is of rising concern is the area adjacent the transistor gates. Typically, the regions adjacent the gates can undergo several ash and clean steps following dopant implantation steps. When silicon is exposed to the oxidizing environment of these conventional ashing processes, a portion of the silicon adjacent the gate, and particularly in the LDD region, is oxidized. The ashing process is conducted for a period of time and at energy levels sufficient to remove the photoresist. It is during this exposure time that the silicon adjacent the gate structures is oxidized. Because of the amount of energy and time associated with such conventional ashing steps and the number of times the ashing steps are conducted, the silicon oxidation can achieve a significant thickness, which consumes a relatively substantial amount of silicon. As the areas adjacent the gates are subjected to clean steps, a portion of the oxidized silicon is removed. After repeating these steps several times, a significant portion of the original silicon substrate is removed to form recesses adjacent the gate. In fact, silicon loss can range from about 5 nm to about 7 nm.
In the past, the lightly doped implant regions were much larger and deeper due to the overall device size, and due to these larger sizes, silicon loss in the LDD regions was not of great concern. However, as devices have shrunk below the submicron range, implants have become much shallower, and in some cases, more lightly doped. As such, any loss of silicon in the LDD regions can lead to dopant loss, Negative Bias Temperature Instability (NBTI) degradation, channel pinch-out, and can generally have a significant negative impact on device performance.
Therefore what is needed in the art is a photoresist removal and clean process that avoids these disadvantages.